Written by an engineer at the leading edge of SiP design and implementation, this book demonstrates how to design SiPs using Mentor EE Flow. Key topics covered include wire bonding, die stacks, cavity, flip chip and RDL (redistribution layer), Embedded Passive, RF design, concurrent design, Xtreme design, 3D real-time DRC (design rule checking), and SiP manufacture. Extensively illustrated throughout, covers an array of issues of vital concern for SiP design and fabrication electronics engineers, as well as SiP users, including: Designed to function equally well as a reference, tutorial, and self-study, is an indispensable working resource for every SiP designer, especially those who use Mentor design tools.